Sense amplifiers are used in memory devices to allow for reduced voltage swing on the bit lines. In a dynamic random access memory (DRAM) circuit, each data bit is stored in a small storage capacitor that is discharged quickly. A sense amplifier detects a signal representing the bit on a bit line and amplifies the signal to an amplitude near the DRAM circuit's supply voltage. The capacitor is recharged as the signal is amplified. The sense amplifier detects and amplifies the signal on a periodic basis, such as every few milliseconds, before the data bit ceases to be detectable.
In a known sense amplifier, a complementary pair of bit lines is precharged to the same potential in preparation for detecting and amplifying the signal representing the data bit. A reset circuit resets the sense amplifier by connecting all its inputs and outputs and the complementary pair of bit lines together to equalize their potentials. After the reset, the data bit is written onto one of the bit lines from the storage capacitor. The sense amplifier amplifies the difference between of voltages across the complementary pair of bit lines. The sensitivity and reliability of the sense amplifier depends on the equilibration of the complementary pair of bit lines during the reset. Because of mismatches in transistor characteristics and offsets in the sense amplifier, an offset voltage develops across the complementary pair of bit lines during the reset/equilibration. This offset voltage may be erroneously detected and amplified by the sense amplifier as a signal representing a data bit. Therefore, the sensitivity and reliability of the sense amplifier are limited.
There is a need for a sense amplifier with improved sensitivity and reliability.